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Cross-node Virtual Machine Communication Acceleration
Micro-architectural Characterization of Desktop Cloud Workloads
Application-driven Energy-efficient Architecture Explorations for Big Data
Efficient data streaming with on-chip accelerators: Opportunities and challenges
Optimization of Stateful Hardware Acceleration in Hybrid Architectures
Frequent Instruction Sequential Pattern Mining in Hardware Sample Data
Compiler and Runtime Techniques for Software Transactional Memory Optimization
Hardware Transactional Memory System for Parallel Programming
Accelerating Sequential Programs On Chip Multiprocessors Via Dynamic Prefetching Thread
A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors
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