WELCOME
Home
Publications
Honors
Academic Services
Experience
Contact
1
Optimization of Stateful Hardware Acceleration in Hybrid Architectures
Frequent Instruction Sequential Pattern Mining in Hardware Sample Data
Compiler and Runtime Techniques for Software Transactional Memory Optimization
Hardware Transactional Memory System for Parallel Programming
Accelerating Sequential Programs On Chip Multiprocessors Via Dynamic Prefetching Thread
A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors
A Memory Bandwidth Effective Cache Store Miss Policy
«
Cite
×